1. Technical Field
This invention generally relates to computer system cache memory and more specifically relates to interfaces for random access cache memories.
2. Background Art
Today, our society is heavily depenent upon computers for everyday activity. Computers are found in homes, in business offices, and in most production and manufacturing environments. Most computer systems are controlled by a central processing unit (CPU) and have various levels of memory which can be used by the CPU to perform the various functions for which it has been programmed. Typically, computer programs are loaded into the computer system's memory storage areas and executed by the CPU. The programs and data are stored in different areas of the computer system's memory depending on what type of function the CPU is performing. Traditionally, the computer system's memory has been classified as either main memory (primary or main storage) or secondary memory (secondary storage). Programs and data need to be in main memory in order to be executed or referenced by a running program, while programs or data not needed immediately may be kept in secondary memory until needed and then brought into main storage for execution or reference.
In the 1960's, it became clear that the traditional memory storage hierarchy could be extended by one more level with dramatic improvements in performance and utilization. This additional level, the "cache," is a high-speed memory that is much faster than the main memory. Cache storage is relatively expensive when compared with main memory and therefore, in a typical computer system, only relatively small amounts cache memory are used. In addition, limiting the size of cache storage enhances the speed of the cache.
Cache memory generally operates faster than main memory, typically by a factor of five to ten times and may, under certain circumstances, approach the operational speed of the CPU itself. By keeping the most frequently accessed instructions and/or data in high speed cache memory, average overall memory access time for the system will approach the access time of the cache. There is a certain amount of overhead involved in shuttling information between various memory locations. This overhead is kept as small as possible so that it does not cancel out the performance increase achieved by utilizing cache storage. In addition, if the specific program instruction to be executed has been pre-loaded into the cache, the CPU may execute the program instruction without returning to either main memory or secondary memory, thereby significantly increasing the operational speed of the system. Whenever the CPU requests a specific instruction or item of data, the CPU generates a request which includes a tag as part of the address or location in memory where the instruction or data may be found. If the tag for the information requested by the CPU matches a tag for a line of memory currently residing in the cache, then the CPU can access the data or instruction from the cache. If the tag doesn't match any of the tags for the lines of memory in the cache, then the information must be fetched and loaded into the cache.
Cache memory may be subdivided into different categories based on what part of the computer system it is located on or associated with. Level 1 cache memory is generally located in the same semiconductor die area that the processor is located. Previously, additional cache memory that is not located on the same chip with the microprocessor is usually referred to as Level 2 cache memory. Currently, more processor designers are locating Level 2 caches on the same semiconductor chip as the processor. Level 3 memory is usually called "main memory," but some computers have Level 3 memory that is cache memory and a Level 4 memory that is main memory.
In the past, caches have been almost exclusively been made of Random Access Memory (RAM) that is static. This Static RAM (SRAM) is made so that the individual cells that contain the bits of data do not have to be refreshed. SRAM, because of the design criteria of maintaining individual cell's datum, takes a large amount of semiconductor area and is relatively expensive, but has high speed. Another competing RAM is Dynamic RAM (DRAM). DRAM is any RAM wherein the cells of data have to be refreshed. Each cell, if not refreshed, will slowly lose its information. The design of DRAM allows it to cover much less area for the same number of bits as SRAM. Additionally, for the same area, DRAM holds many more bits of information than does SRAM. Unfortunately, because each cell in a DRAM array needs to be refreshed periodically, there are times when a particular cell or group of cells cannot be written or read because refresh is occurring.
Recently, because of the high number of data bits that are able to be placed in a small area for DRAM, some designers have used DRAM in L2 caches. For instance, in U.S. Pat. No. 5,829,026, "Method and Structure for Implementing a Cache Memory Using a DRAM Array," by Leung, et al., a DRAM cache that can be on or off the same chip as that holding the processor is disclosed. Also, in U.S. Pat. No. 5,895,487, entitled "Integrated Processing and L2 DRAM cache," by Boyd, et al., an L2 DRAM cache is disclosed that is located on the same semiconductor chip as the processor. Embedded DRAM (EDRAM) is DRAM that is created from logic technology that has less density than normal drams but has access times that are approaching SRAM access times.
When designing a semiconductor chip having a processor and an off- or on-chip L2 cache, it would beneficial to have an option as to whether the L2 cache is SRAM or DRAM. Unfortunately, the previously discussed patents only provide a cache interface that interfaces with DRAM (or DRAM). Similarly, cache interfaces for SRAM only interface with SRAM.
Additionally, current cache interfaces do not provide any programmability. For systems having SRAM caches, in particular, a designer who wishes to add an SRAM cache that is a certain size and speed must create an interface for this particular size and speed of SRAM cache. If the size or speed of the SRAM cache is changed during the next version of the processor, the interface must be redesigned. Likewise, if the designer wishes to en large a DRAM cache, he or she must redesign the cache interface.
These problems are particularly egregious in today's processor marketing environment, where processor manufacturers like to sell multiple versions of the same processor, each version having a different amount and/or speed of cache.
Although there are SRAM and DRAM cache interfaces, there exists a need to provide a programmable cache interface that supports both SRAM and DRAM caches. Additionally, designers are currently burdened with creating new cache interfaces whenever the size or speed of the cache changes; consequently, a programmable cache interface that allows the size and speed of the cache to be easily changed is needed.